module pipelined_mac #(
    parameter WIDTH = 8
)(
    input  wire                  clk,
    input  wire                  reset,
    input  wire [WIDTH-1:0]      a,
    input  wire [WIDTH-1:0]      b,
    // [(WIDTH*2):0] in case of overflow
    output reg  [(WIDTH*2):0]    accumulator
);

    reg [(WIDTH*2)-1:0] mult_reg;

    always @(posedge clk) begin
        if (reset) begin
            mult_reg    <= 0;
            accumulator <= 0;
        end else begin
            // multiplication
            mult_reg    <= a * b;

            // accumulation
            accumulator <= accumulator + mult_reg;
        end
    end

endmodule